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NCP5680
PIN DESCRIPTIONS
Pin
10
Name
Vds1
Type
INPUT,
ANALOG
Description
This pin fulfils three functions:
? support the I ? LED when the Torch mode is activated. In this case, the Gate drive Vgs1and
Vgs2 signals are deactivated. The internal current mirror, programmed by the I2C port, limits the
ILED2 to 100 mA maximum
? support the Indicator LED current when this mode is activated. In this case, the Vgs1 and Vgs2
signals are deactivated. The internal current mirror, programmed by the I2C port, limits the ILED1
to 20 mA maximum
? sense the Drain voltage across the external NMOS #2 to detect the overload condition: see
Table 2.
11
12
13
14
15
16
17
18
19
Is1
Vgs1
AGND
Vbias
SCAP
Vg ICH
Is ICH
PGND
Vout
INPUT,
ANALOG
OUTPUT,
POWER
OUTPUT,
POWER
OUTPUT, Bias
INPUT,
ANALOG
OUTPUT,
ANALOG
INPUT,
ANALOG
OUTPUT,
POWER
OUTPUT,
POWER
This pin, associated to Vgs1 and the Vout pin, returns the sense voltage, developed across the
external shunt resistor, to the LED#1 current control loop. Care must be observed to avoid noise,
stray capacitance and parasitic ohmic element between shunt resistor and this point to minimize
the parasitic pulses on the LED output current.
This pin controls the gate of the external NMOS device and the LED is activated when the bit
BLED0=1 in the Select Register byte. Care must be observed to minimize the routing between
this pin and the gate of the external device. Similarly, the PCB track shall be designed to sustain
the relative high current pulse flowing into the Ciss during the normal operation. The built ? in
driver structure is capable to control 10A rated NMOS device with Ciss up to 2500 pF.
This pin carries the return to ground of the analog and digital blocks and must be connected to
the external ground plane.
This pin provides the bias voltage necessary to drive the supercap capacitor. The Vbias voltage
is equal to Vout/2 and shall not be overloaded.
This pin senses the voltage developed across the external SuperCAP. This voltage is fed back to
the Vbias network to maintain the appropriate bias voltage at the superCAP mid point.
This pin drives the gate of the external PMOS associated to the superCAP current control loop.
Such a function might be omitted when not necessary in the final application. In this case, a direct
contact can be set ? up between the Vout pin and the external SuperCAP capacitor, the current
being limited to 500 mA maximum.
This pin, associated with the Vg ICH signal, is the return of the SuperCAP charge current sense.
An external shunt resistor shall be connected between Vout and the external PMOS drain to
monitor the superCAP charge current.
These pins carry the ground return of the DC/DC converter and must be connected to the extern-
al ground plane. Since this pin provides the current charge path for the external Super Cap capa-
citor, cares must be observed to minimize both the ESR and the ESL parasitic elements between
the Super cap negative electrode and these pins. Using ground plane technique is highly recom-
mended.
This pin provides the output voltage supplied by the DC/DC converter and must be bypassed by
a 10 m F ceramic capacitor minimum located as close as possible to the pin. The circuit shall not
operate without such bypass capacitor properly connected to the Vout pin.
The converter supplies 500 mA maximum continuous current to total external load. Con-
sequently, the re ? cycling time depends upon the Super Cap capacitance value, the operating
Vbat input supply voltage and the programmed I ICH .
The output voltage is internally clamped to 5.5 V maximum in the event of no load situation. On
the other hand, the output current is limited to 100 mA (maximum) in the event of a short circuit to
ground.
20
21
22
23
24
C2P
C2N
C1P
C1N
Vbat
POWER
POWER
POWER
POWER
INPUT,
POWER
One side of the external charge pump capacitor (C FLY ) is connected to this pin, associated with
C2N pin.
One side of the external charge pump capacitor (C FLY ) is connected to this pin, associated with
C2P.
One side of the external charge pump capacitor (C FLY ) is connected to this pin, associated with
C1N pin.
One side of the external charge pump capacitor (C FLY ) is connected to this pin, associated with
C1P.
This pin is connected to the input Battery voltage to supply all the built ? in blocks. The pin must be
connected to the Power plane and decoupled to ground by a 10 m F ceramic capacitor minimum.
1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the Charge Pump efficiency and to reduce the EMI. Care must be
observed to prevent large influence of the ceramic capacitor DC bias: using 10 V rated capacitor, 0805 or 0603 size, is recommended.
2. Total DC/DC output current is limited to 500 mA
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